The present invention relates generally to integrated circuit designs and more particularly to a system for controlling power to an integrated circuit module such as a static random access memory (SRAM).
Random access memory (RAM) is typically used for temporary storage of data in a computer system. There are several types of RAM, including dynamic random access memory (DRAM) and SRAM. An SRAM circuit retains its memory state without requiring any data refresh operations as long as power is supplied to the SRAM circuit. A basic SRAM cell may consist of two cross coupled inverters and two access transistors connecting the two inverters to complementary bit-lines. The two access transistors are pass-transistors, controlled by word-lines to select the cell for read or write operations. In read operation, the access transistors are switched on to allow the charges retained at storage nodes of the cross coupled inverters to be read via the bit line and its complement. In write operation, the access transistors are switched on and the voltage on the bit line and the complementary bit line are charged to a certain level to change the memory state of the cell. The SRAM cell retains one of its two possible steady states of “0” and “1” when the two pass transistors are turned off. Reading from and writing to a SRAM cell requires that the voltages on the bit-lines be sufficient to change (or “flip”) the logical state of the two inverters during the time the access transistors are turned on. Conventionally, a memory cell is designed to operate with a lower supply voltage in the write operation than in the read operation because lowering the supply voltage increases the write margin of the memory cell.
FIG. 1 shows one type of conventional circuit 100 for lowering the supply voltage to an array of SRAM cells. A power control circuit 110 is connected to a core voltage supply (CVDD) and provides an intermediate supply voltage (CVDDi) to the SRAM array 120. A signal A controls PMOS device P1, such that P1 acts as a power switch between CVDD and CVDDi. In normal operation, signal A is a logical “low” such that the PMOS device P1 is turned on and CVDD is coupled to CVDDi without a substantial voltage drop. In this mode, PMOS device P2 is substantially cutoff and is non-conducting. In write operation, the signal A is raised to a logical “one” such that the PMOS device P1 is turned off and the PMOS device P2 operates as a diode to provide a voltage drop between the CVDD and CVDDi thus lowering CVDDi.
One skilled in the art would appreciate that in the conventional design of FIG. 1, there is no mechanism to determine if the operating voltage of the SRAM array is low enough to provide a reliable write operation. Accordingly, there is a need for a power control circuit that can reliably adjust the operating voltage of an integrated circuit module such as a memory cell at a desired level.